1. Field of the Invention
This invention concerns a complementary signal output circuit which supplies complementary signals which are in-phase with and anti-phase to an input signal.
2. Description of the Prior Art
FIG. 1 is a block diagram of a conventional complementary signal output circuit for obtaining mutually anti-phase complementary signals which are used as, e.g., clock signals for logic circuits.
The complementary signal output circuit of FIG. 1 is constructed from inverter circuits I1-I4 composed of, for instance, CMOS circuits. An input signal IN is received by the inverter circuit I1, and inverted thereby. The output signal of the inverter circuit I1 is inverted by the inverter circuit I2. Then, the output signal of the inverter circuit I2 is inverted by the inverter circuit I3, and the output of the inverter circuit I3 is obtained as an anti-phase signal .phi. which is anti-phase to the input signal IN. At the same time, the output signal of the inverter circuit I1 is inverted by the inverter circuit I4, and the output signal of the inverter circuit I4 is obtained as an in-phase signal .phi. which is in-phase with the input signal.
Therefore, in this circuit, whereas the anti-phase signal .phi. is obtained by an odd number of inverter circuits I1, I2 and I3 which are cascade-connected to the input signal IN, the in-phase signal .phi. is obtained by an even number of inverter circuits I1 and I4 which are cascade-connected to the input signal IN. That is to say, while the in-phase signal .phi. is outputted with a delay time of 2 stages of inverter circuits with respect to the input signal IN, the anti-phase signal .phi. is outputted with a delay time of 3 stages of inverter circuits with respect to the input signal IN. Thus, as shown by the operating wave-form diagram in FIG. 2, the anti-phase signal .phi. is delayed by one more stage of inverter circuit when compared with the in-phase signal .phi..
Thus, there is a problem of different switching times between the in-phase signal .phi. and the anti-phase signal .phi. in the prior art, which sometimes causes a misoperation of the circuit being supplied with the signals.